With nanowire-based field effect transistors (FETs), the nanowires serve as channels of the device interconnecting a source region and a drain region. A gate surrounding the nanowire regulates electron flow through the channels. When the gate completely surrounds a portion of each of the nanowire channels, this configuration is referred to as a gate-all-around (GAA) device. GAA nanowire-based FETs have excellent scaling properties and are presently investigated as building blocks for future complementary metal-oxide semiconductor (CMOS) technology.
Process-induced channel strain is presently used to enhance device performance. Namely, compressive strain is used with p-channel FETs (PFETs) to improve the hole mobility and tensile strain is used with n-channel FETs (NFETs) to improve the electron mobility. While the techniques for inducing channel strain in planar CMOS devices are relatively straightforward, this is not the case with nanowire-based devices. Applying channel strain in the case of nanowire FETs is challenging.
Therefore, process-induced channel strain techniques for GAA nanowire-based FETs would be desirable.